Regardless of the type of information processing system, various basic functions are common in various forms to all these systems. These basic functions are effected by various structural, hardware and software elements of the information processing system. In simplified form, let it be assumed that this information processing system is a conventional computer comprising a central processor unit or CPU, also known as a host system, and various peripheral devices, which are either magnetic peripherals such as disk memories or tape drives, or input/output peripherals enabling the exchange of data with the outside (such as printers and various screen terminals, etc).
The central unit or host system is embodied by at least one central processor unit (or in the case of the information processing system of the multiprocessor type, by a plurality of processors) and a main memory to which the processor or processors are connected, and one or more input/output processors that assure the monitoring of the exchange of data between the memory and the various peripherals.
The physical transfer of data between the CPU and the peripheral or peripherals associated with it is performed by way of a coupler (or couplers) connected on the one hand to the output bus of the CPU and on the other to the peripheral that is to be used.
All the constituent functional elements comprising an information processing system, that is, CPUs or input/output processors, random-access memories and read-only memories, input/output controllers or peripheral controllers, are disposed on a set of boards, the dimensions of which are generally standardized. Each board comprises a printed circuit, on which a plurality of integrated circuits or chips are disposed, each of them comprising well-defined functional systems or subsystems manufactured on a large scale by the various manufacturers of electronic components, such as Texas Instruments, Motorola, Intel, and so on.
These boards are generally connected to the same parallel bus, which assures communications among the various processors, the transfer of data between the various boards, and the supply of electricity to the boards. To this end, the boards are provided with male plugs (generally two plugs) making it possible to connect them physically to the bus, which in turn has corresponding female plugs disposed at a certain number of predetermined connection sites, or slots.
The bus commonly known as Multibus II (a trademark of the Intel Corporation) is presently among the most often-used buses in the industry. This bus is the product of work by a group including 17 other American and European corporations besides Intel. Among these corporations are AMD, Tektronics, Hewlett-Packard, ICL, Siemens, the present assignee company, and others. This Multibus II exhibits good performance as well as great versatility and reliability in use.
As its name indicates, the architecture of a Multibus II is structured around a plurality of buses and includes one main bus and secondary buses. Only the main bus is standardized by the IEEE standard-1296 (IEEE stands for the Institute of Electrical and Electronic Engineers), and only this bus pertains to the invention.
This bus is called a PSB (for parallel system bus). It is intended for general use and is designed to operate in a multiprocessor environment, with functions of arbitration, board identification, etc.
The PSB is constructed on the "Double Europe" board format (233.times.220 mm), with two plugs called P.sub.1 and P.sub.2, one of which corresponds to the PSB and the other of which is free.
The two plugs are 96-pin models (with three parallel rows of 32 pins) meeting the standards defined by the International Electromechanical Commission in category 603-2IEC096, pertaining to male plugs present on each of the boards, or female plugs disposed on the bus itself. These 96-pin plugs are also defined by DIN standard 41612.
The PSB bus system assures interprocessor communications and data movement. It accepts any type of processor presently available on the market. It has the following characteristics:
An output of 40 megabytes per second in the burst mode, obtained by a clock frequency of 10 MHz for a bus width of 32 bits (in other words 4 8-bit bytes);
Synchronous function, which cancels out the influence of parasitic signals whenever it is inactive; and
The capability of working with 8-, 16- or 32-bit processors or of transferring data over 8, 16, 24 or 32 bits.
The Multibus II is a basket type of bus. This means that it is embodied by a printed circuit that carries plugs; IEEE standard 1296 defines each of the conductors that composes it, the dimensions of the boards connected over the bus, the spacing between them, their mechanical characteristics, and so forth. The number of boards that can be connected on the Multibus II is also limited to 20, because with a greater number of boards the performance, or power, is limited by the greater dissipation of energy, the existence of parasitic capacitance and inductance, and so forth. The length of the bus is also limited to 40 cm.
The physical structure of a multiprocessor information processing system architecture is accordingly in the form of a board-carrying basket including a plurality of logic boards (a maximum of 20 for a basket including a Multibus II), of substantially parallelpiped form. The bottom of the basket has a substantially rectangular shape. The basket bottom carries the Multibus, which takes the form of an oriented copper printed circuit that includes a plurality of connection sites (20 in number) on which female 96-pin plugs are disposed. The sides of the basket parallel to its length and perpendicular to the bottom of the basket each include one row of board guides parallel to the inside by which the boards can slide, in order to be connected by the male plugs to the female plugs disposed on the bottom of the basket.
When information processing system architecture designers develop the electronic assembly plans comprising these systems (that is, the set of boards that comprise them), their objectives include both better availability for the information processing system, and good performance.
It will be recalled that for an information processing system, unavailability, or "down time", is the time during which the system or subsystem is unavailable to the customer using it (because of a breakdown, or repair, for general overhaul of the system, for instance). Hence "availability" is defined as the opposite of unavailability.
On the other hand, performance of a predetermined system means the number of transactions it can perform per unit of time. For example, for a disk memory, performance is established by measuring the number of reading and writing operations that can be done during the unit of time (seconds, microseconds, etc.). If availability and high performance are sought, then the problem of doubling the bus is encountered, that is, of achieving an information processing system architecture including two identical electronic sets, each constructed about the same bus, such as a Multibus II type of bus. The physical structure of such a system thus comprises two identical board-carrying baskets. The resultant new architecture, composed of two identical sets, thus provides the desired redundancy, and enables increasing both availability and performance compared with the structure including only a single set.
For internal handling of cases of partial breakdown (these are breakdowns that may arise in some or all of the physical elements comprising the above-defined electronic sets) not by the software of the central processing unit of the information processing system but instead by software contained in one of the aforementioned physical elements, a physical connection is then made between each of the two electronic sets that comprise the architecture of the information processing system.
The connection between the two sets is most powerful when it in fact becomes a third bus over which elements common to the two sets are connected. The disadvantage of this system is that it includes at least two additional boards to make the connection between the two sets, that is, a first connection board connected to the first bus of the first set, and a second board connected to the second bus of the second set. Moreover, if the third bus breaks down, in whatever area, the advantage obtained is then lost: genuine double access, which is intended for the sake of availability, is then no longer available to either the first set or the second set.
Another disadvantage that should also be mentioned is the necessity of connecting the two baskets including the two electronic sets by the same cable, which is relatively expensive and lowers performance.